This invention relates to a semiconductor memory device and more particularly to isolation transistors and a circuit for controlling the isolation transistors.
As semiconductor memory devices become more highly integrated, the structures of the memory arrays have been improved. Further, there have been proposed various techniques for arranging bit lines, such as an open bit line scheme, a folded bit line scheme and a shared bit line scheme. In general, the structures of the memory cell arrays are designed in consideration of the bit line arrangement.
Recently, to further increase integration density of memory chips, semiconductor memory is designed such that adjacent first and second memory cell array blocks share a common bit line sensing amplifier. In order to access data from a selected one out of the first and second memory cell array blocks, an unselected memory cell array block is temporarily electrically isolated from the common bit line sensing amplifier by controlling isolation transistors.
Korean patent application No. 1991-10195 filed by Samsung Electronics on Jun. 19, 1991 discloses how to improve operational characteristics of the sense amplifier in a semiconductor memory using isolation transistors. Moreover, Korean patent application No. 1991-20914 also filed by Samsung Electronics on Nov. 22, 1991, discloses improved isolation transistors. The device has advantages of high operation speed and low current consumptions. However, a problem occurs with this device during a burn-in mode. The high voltage continuously applied to the gates of the isolation transistors during the burn-in operation result in the destruction of the gate oxide layers of the isolation transistors.
It is most important in designing these isolation transistors to allow the isolation transistors to pass data output from a memory cell array to the sense amplifier or input/output lines without voltage drops. Destruction of the gate oxide layers prohibit this important design consideration from being met.
Referring to FIG. 1, neighboring memory cell array blocks, out of four memory cell array blocks MCAi, MCAj, MCAk and MCAl, share a sense amplifier disposed therebetween through isolation transistors IT1-IT12 each controlled by isolation control signals ISOi, ISOj, ISOk and ISOl. It is noted from FIG. 1 that the isolation control signals ISOi, ISOj, ISOk and ISOl are generated from the isolation control signal generating circuits 10, 20, 30 and 40, each of which is controlled by the block selection address signals DRAi, DRAj, DRAk and DRAl that correspond to the memory cell array blocks MCAi, MCAj, MCAk and MCAl. The isolation control signals control the isolation transistors IT1-IT12 connected to the memory cell array blocks adjacent thereto.
FIG. 2, showing the operational timing diagram of the FIG. 1 circuit, will now be used to explain operation of the circuit. When none of memory cell array blocks are selected, the block selection address signals DRAi, DRAj, DRAk and DRAl are all at the logic "high" state of power supply voltage level (herein after referred to as "Vcc level"). Then, the isolation control signals ISOi, ISOj, ISOk and ISOl all become the logic "high" state of the boost voltage level (hereinafter referred to as "Vpp level", so that the isolation transistors IT1-IT12 are provided with the boost voltage Vpp at the gates thereof and are all turned on. Here, the boost voltage Vpp is higher than the externally power supply voltage Vcc. If the memory cell array block MCAj is selected, the block selection address signal DRAj for designating the block MCAj changes to the logic "low" state. Then, NMOS transistors 2 and 4 in the isolation control signal generating circuit 20 are respectively turned off and turned on, so that the voltage at a node 6 is discharged from the boost voltage Vpp to the ground voltage Vss. Thus, the isolation control signal ISOj becomes the logic "low" state. Therefore, the isolation transistors IT1, IT2, IT7 and IT8 whose gates are commonly connected to the isolation control signal ISOj are turned off and the other isolation transistors IT3, IT4, IT5, IT6, IT9, IT10, IT11 and IT12 are all turned on. As a result, the memory cell array blocks MCAi and MCAk are isolated from the sense amplifiers. In this way, the data stored in the memory cell array block MCAj can be sensed by the sense amplifiers.
In the conventional device, the isolation control signals ISOi, ISOj, ISOk and ISOl fully swing between the boost voltage Vpp and the ground voltage Vss, resulting in large current consumptions and operational speed loss. Such drawbacks become more serious when the conventional device is applied to the high density semiconductor memory having small sized transistors and using low operational voltage. Furthermore, since the isolation transistors IT9, IT10, IT11 and IT12 of the unselected memory cell array block MCA1 are provided with the boost voltage Vpp at the gates thereof, the isolation transistors are under the stress of high voltage. In particular, when the device operates in a burn-in mode, where the high voltage such as the boost voltage Vpp is applied externally to check the performance of the memory chip under the high voltage stress, the isolation transistors will be under the large stress of the high voltage, causing the destruction of the gate oxide layers of the isolation transistors.
FIG. 3, illustrates another known device disclosed in "1992 Symposium on VLSI Circuits Digest of Technical Papers, pp. 106-107, entitled "Application of High-Voltage Pumped Supply for Low-Power DRAM" by R. C. Foss. In this device, the isolation transistors are provided with the power supply voltage VDD during a normal state, and with the boost voltage Vpp during a data access cycle. However, during the burn-in mode, the isolation transistors will still be under the stress of the high boost voltage, causing the destruction or deterioration of the gate oxide layers of the isolation transistors.